1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a charge pump circuit generating a boosted potential or a negative potential from a power supply potential supplied from the exterior and a nonvolatile semiconductor memory device comprising the same.
2. Description of the Prior Art
A semiconductor device such as a flash memory electrically writing, reading or erasing data generates a plurality of potentials in its interior in addition to a power supply potential which is supplied from the exterior, for writing, reading or erasing data through these potentials.
In the flash memory, for example, each memory cell is formed by a single transistor having a drain and a control gate which are connected to a bit line and a word line respectively. The flash memory erases data by applying a positive high potential to the control gate of the transistor forming the memory cell while applying a negative high potential to the source and a P well thereby injecting electrons into a floating gate through the F-N (Fowler-Nordheim) tunnel effect.
On the other hand, the flash memory writes data by applying a negative high potential to the control gate while applying a positive high potential to the drain thereby extracting electrons from the floating gate through the tunnel effect.
Internal potentials employed in respective operations of a conventional flash memory are now described.
FIGS. 44A and 44B are adapted to illustrate potentials supplied to each memory cell of the conventional flash memory in respective modes.
In an erase operation for a selected block, a source potential Vs, a control gate potential Vcg and a potential BG of a well part (hereinafter referred to as a back gate) forming a channel of a transistor are -11 V, 12 V and -11 V respectively, and a drain potential Vd is in a floating state (Z) as shown in FIGS. 44A and 44B.
In a write operation for the selected block, the source potential Vs is in a floating state (Z), and the control gate potential Vcg, the back gate potential BG and the drain potential Vd are -11 V, 0 V and 5 to 9 V (set in units of 0.3 V) respectively.
In an OP (over-program) recovery operation for returning a threshold value into a normal range for recovering the selected block from an overwritten state, the source potential Vs, the control gate potential Vcg, the back gate potential BG and the drain potential Vd are 0 V, 6 V, 0 V and 8 V respectively.
In a read operation for the selected block, the source potential Vs, the control gate potential Vcg, the back gate potential BG and the drain potential Vd are 0 V, 3 V, 0 V and less than 1 V respectively.
When a power supply potential which is supplied from the exterior is only 3 V, therefore, the flash memory generally comprises a plurality of positive and negative potential generation circuits containing charge pump circuits therein, in order to generate the potentials of 12 V, 5 to 9 V, 8 V, 6 V and -11 V through the power supply potential respectively.
FIG. 45 is adapted to illustrate potentials generated by the charge pump circuits in the respective modes of the conventional flash memory.
Referring to FIG. 45, the conventional flash memory comprises three positive potential generation charge pump circuits generating positive potentials VPL, VPM and VPS respectively and a negative potential generation charge pump circuit generating a negative potential VN.
In case of erasing data in any memory cell, the positive and negative potentials VPL and VN are 12 V and -11 V respectively, while the positive potentials VPM and VPS are not used. The positive potential VPL is supplied to a selected word line. The negative potential VN is supplied to a well formed with a memory cell transistor and the source of the memory cell transistor.
In case of writing data in any memory cell, the positive potentials VPL and VPM are 12 V and 5 to 9 V respectively, and the negative potential VN is -11 V, while the positive potential VPS is not used. The positive potentials VPL and VPM and the negative potential VN are supplied to a selected selector gate line, a selected main bit line and a word line of a memory transistor respectively.
In OP recovery, the positive potentials VPL, VPM and VPS are 12 V, 8 V and 6 V respectively, while the negative potential VN is not used. The positive potentials VPL, VPM and VPS are supplied to a selected selector gate line, a selected main bit line and a word line of a memory transistor respectively.
As understood from the above description, the positive potential VPS and the negative potential VN are not simultaneously required in any operation. If a single circuit is servable both as the positive and negative potential generation charge pump circuits for generating the positive potential VPS and the negative potential VN, therefore, the area for a single charge pump circuit can be reduced.
FIG. 46 is a circuit diagram showing the structure of a conventional charge pump circuit for generating positive and negative potentials disclosed in Japanese Patent Laying-Open No. 7-177729 (1995).
Referring to FIG. 46, the conventional charge pump circuit for generating positive and negative potentials includes a P-channel MOS transistor 816, receiving a control signal P-IN in its gate, which is connected between a power supply potential Vcc and a node L, a diode 801 having an anode and a cathode which are connected to the node L and a node A respectively, a diode 802 having an anode and a cathode which are connected to the node A and a node B respectively, a diode 803 having an anode and a cathode which are connected to the node B and a node C respectively, a diode 804 having an anode and a cathode which are connected to the node C and a node D respectively, a diode 805 having an anode and a cathode which are connected to the node D and a node E respectively, a diode 806 having an anode and a cathode which are connected to the node E and a node F respectively, a diode 807 having an anode and a cathode which are connected to the node F and a node M respectively, and an N-channel MOS transistor 817, receiving a control signal N-IN in its gate, which is connected between a ground potential GND and the node M.
The conventional charge pump circuit for generating positive and negative potentials further includes a capacitor 840 connected between a clock node which is supplied with a clock signal PH and the node A, a capacitor 841 connected between a complementary clock node which is supplied with a clock signal/PH, complementary to the clock signal PH, and the node B, a capacitor 842 connected between the clock node and the node C, a capacitor 843 connected between the complementary clock node and the node D, a capacitor 844 connected between the clock node and the node E, and a capacitor 845 connected between the complementary clock node and the node F.
Operations of the conventional charge pump circuit for generating positive and negative potentials are now briefly described.
In case of generating a positive potential VHP, the control signal P-IN is activated and the P-channel MOS transistor 816 conducts to supply the power supply potential Vcc to the node L. On the other hand, the control signal N-IN is inactivated and the N-channel MOS transistor 817 enters a non-conducting state. A voltage responsive to the amplitude of the clock signals PH and/PH and the stage number of the diodes 801 to 807 is generated by a charge pump operation to cause a constant potential difference between the nodes L and M. Since the node L is supplied with the power supply potential Vcc, the potential of the node M reaches a constant level which is higher than the power supply potential Vcc, to provide the positive potential VHP.
In case of generating a negative potential VHN, on the other hand, the control signal N-IN is activated and the N-channel MOS transistor 817 conducts to supply the ground potential GND to the node M. On the other hand, the control signal P-IN is inactivated and the P-channel MOS transistor 816 enters a non-conducting state. A voltage responsive to the amplitude of the clock signals PH and/PH and the stage number of the diodes 801 to 807 is generated to cause a constant potential difference between the nodes L and M. Since the node M is supplied with the ground potential GND, the potential of the node L reaches a constant level which is lower than the ground potential GND, to provide the negative potential VHN.
FIG. 47 is a sectional view for illustrating the structures of diode elements employed as some of the diodes 801 to 807 in FIG. 46.
In case of employing MOS transistors as diodes in general, diode-connected N-channel MOS transistors are employed as diode elements for forming a charge pump circuit for generating a positive voltage, while diode-connected P-channel MOS transistors are employed as diode elements for forming a charge pump circuit for generating a negative potential.
When MOS transistors are employed as diode elements, therefore, no common voltage generation part is applicable to charge pumping for generating both positive and negative potentials.
In order to implement the circuit shown in FIG. 46, therefore, PN junction diodes formed on an SOI substrate are employed.
Referring to FIG. 47, an SOI substrate 852 comprises an insulator film 856 which is formed on a silicon substrate 854. Diodes 801 to 803 which are PN junction diodes are formed on the insulator film 856.
The diode 801 includes a P-type impurity region 801a and an N-type impurity region 801b. The diode 802 includes a P-type impurity region 802a and an N-type impurity region 802b. The diode 803 includes a P-type impurity region 803a and an N-type impurity region 803b.
The P-type and N-type impurity regions 801a and 801b are connected to a power supply potential Vcc and a node A respectively. The P-type and N-type impurity regions 802a and 802b are connected to the node A and a node B respectively. The P-type and N-type impurity regions 803a and 803b are connected to the node B and a node C respectively.
A capacitor 840 is connected between the node A and a node receiving a clock signal PH, and a capacitor 842 is connected between the node B and a node receiving a clock signal/PH.
When such a structure is employed, the diodes can be electrically isolated from each other, to be capable of sharing a charge pump part for generating positive and negative voltages.
Also in the flash memory, memory cells, peripheral circuits and the like are reduced in size following refinement year by year, similarly to a dynamic random access memory. Among the peripheral circuits, however, particularly a charge pump circuit must ensure a capacitor size which is necessary for current consumption and a stage number which is necessary for generating a high voltage, and hence it is difficult to reduce the charge pump circuit in size.
The reasons for this are as follows: Since the F-N tunnel effect is utilized for writing/erasing data in any memory cell, it is necessary to reduce the thickness of a tunnel oxide film of the memory cell in order to suppress a voltage necessary for writing/erasing. In consideration of reliability, however, such reduction of the thickness of the tunnel oxide film is limited. Further, a constant area is necessary for ensuring the capacitance of the capacitor.
Following refinement, therefore, the ratio of the occupied area of the charge pump circuit in the chip is disadvantageously increased.
In the conventional technique of employing a common charge pump circuit for generating positive and negative voltages for reducing the area thereof, further, the fabrication cost is disadvantageously increased as compared with the case of employing a general silicon substrate, due to the employment of an SOI substrate.
When PN junction diodes (hereinafter referred to as poly-diode elements) of polysilicon are employed as diodes in order to solve this problem, no problem of a latch-up phenomenon or the like arises dissimilarly to the case of employing MOS diodes. In this case, however, aluminum interconnections are directly brought into electrical contact with the poly-diode elements. Therefore, reaction takes place in the interfaces between the aluminum interconnections and the poly-diode elements to disperse contact resistance, disadvantageously leading to dispersion of the characteristics of the poly-diode elements. Further, the conventional poly-diode elements are weak against electrical noise such as surge or contamination.